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AS1530, as1531 12-bit, single-supply, low-power, 400/300ksps, 8-channel a/d converters data sheet www.austriamicrosystems.com revision 1.02 1 - 29 1 general description the AS1530/as1531 are low-power,8/4-channel, 400/ 300ksps, 12-bit analog-to-digital (a/d) converters specif- ically designed to operate with single-supply devices. superior ac characteristics, very low power consump- tion, and highly-reliable packaging make these ultra- small devices perfect for battery-powered remote-sen- sor and data-acquisition devices. the successive-approximation register (sar), high- speed sampling, high-bandwidth track/hold circuitry, and multi-mode operation combine to make these devices highly-flexible and configurable. both devices require low supply current (2.8ma @ 400ksps, AS1530; 2.2ma @ 300ksps, as1531) and fea- ture a reduced-power mode and a power-down mode to lower power consumption at slower throughput rates. the devices operate from a single supply (+4.5 to +5.5v, AS1530; +2.7 to +3.6v, as1531). both devices contain an internal 2.5v reference, an integrated reference buffer, and feature support for an external reference (1v to v dd ). data accesses are made via the high-speed, 4-wire, spi, qspi-, and microwire-co mpatible serial interface. the devices are available in a 20-pin tssop package. figure 1. block diagram and pin assignments 2 key features single-supply operation: - +4.5 to +5.5v (AS1530) - +2.7 to +3.6v (as1531) sampling rate: - 400ksps (AS1530) - 300ksps (as1531) software-configurable analog input types: - 8-channel single-ended - 8-channel pseudo differential referenced to com - 4-channel pseudo differential - 4-channel fully differential software-configurable input range internal +2.5v reference low-current operation: - 2.8ma @ 400ksps (AS1530) - 2.2ma @ 300ksps (as1531) - 0.4ma in reduced-power mode - 0.5a in full power-down mode spi/qspi/microwire/tms320-compatible 20-pin tssop package 3 applications the devices are ideal for remote sensors, data-acquisi- tion and data-logging devices, pen-digitizers, process control, or any other space- limited a/d application with low power-consumption requirements. AS1530/ as1531 control logic output shift register 12-bit sar in out ref analog input +1.2v ref input shift register track/ hold 17k av 2.05 +2.50v 15 sstrb 17 csn 14 dout 20 v dd1 19 v dd2 13 gnd 18 sclk 16 din 1:8 ch0:ch7 9 com 12 refadj 11 ref 10 v dd3 AS1530/ as1531 1 ch0 2 ch1 3 ch2 4 ch3 5 ch4 6 ch5 7 ch6 8 ch7 9 com 10 v dd3 20 v dd1 19 v dd2 18 sclk 17 csn 16 din 15 sstrb 14 dout 13 gnd 12 refadj 11 ref
www.austriamicrosystems.com revision 1.02 2 - 29 AS1530/as1531 data sheet contents 1 general description ........................................................................................................ ........................ 1 2 key features ............................................................................................................... ........................... 1 3 applications ............................................................................................................... ............................. 1 4 pinout ..................................................................................................................... ................................ 3 pin assignments ............................................................................................................... ...................................... 3 pin descriptions .............................................................................................................. ....................................... 3 5 absolute maximum ratings .. ................................................................................................. ................. 4 6 electrical characteristics ................................................................................................. ....................... 5 AS1530 electrical characteristics ......................... .................................................................... ............................. 5 as1531 electrical characteristics ......................... .................................................................... ............................. 7 timing characteristics ............ ............................................................................................ .................................... 9 7 typical operating characteristics ................ .......................................................................... ............... 11 8 detailed description ....................................................................................................... ...................... 14 analog input .................................................................................................................. ....................................... 14 input protection .............................................................................................................. ............................... 14 track/hold .................................................................................................................... ........................................ 14 control register .............................................................................................................. ..................................... 15 analog input configuration .................................................................................................... ............................... 15 channel selection .......... .............. .............. .............. .............. ........... ........... ............ ......... ................................... 16 single-ended input ........ .............. .............. .............. .............. ........... ........... ........... ........... ............................ 16 differential input ............................................................................................................ ................................ 16 starting a conversion ......................................................................................................... .................................. 17 transfer functions ............................................................................................................ .................................... 18 power modes ................................................................................................................... .................................... 19 reduced power mode .......................................... .................................................................. ....................... 20 full power-down mode .......................................................................................................... ....................... 20 reference ..................................................................................................................... ........................................ 21 internal reference ............................................................................................................ ............................. 21 external reference ............................................................................................................ ........................... 22 9 application information .................................................................................................... ..................... 23 initialization ........................ ........................................................................................ ........................................... 23 serial interface .............................................................................................................. ....................................... 23 serial interface configuration ................................................................................................ ........................ 23 qspi interface ................................................................................................................ ............................... 24 quick evaluation circuit ................................ ...................................................................... ................................. 25 layout considerations ......................................................................................................... ................................. 26 10 package drawings and markings ............................................................................................. .......... 27 11 ordering information ..... ................................................................................................. ..................... 28
www.austriamicrosystems.com revision 1.02 3 - 29 AS1530/as1531 data sheet - pinout 4 pinout pin assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin number pin name description 1:8 ch0:ch7 analog sampling inputs. these eight pins serve as analog sampling inputs. 9com common analog inputs . tie this pin to ground in single-ended mode. 10 v dd3 positive supply voltage 11 ref reference-buffer output /a/dc reference input . this pin serves as the reference voltage for analog-to-digital conversions. in internal reference mode, the reference buffer provides a +2.50v nominal output, externally adjustable at pin refadj. in external reference mode, disable the internal buffer by pulling pin refadj to v dd1 . 12 refadj reference-buffer amplifier input . to disable the reference-buffer amplifier, tie this pin to v dd1 . 13 gnd analog and digital ground 14 dout serial data output . data is clocked out at the rising edge of pin sclk. dout is high impedance when csn is high. 15 sstrb serial strobe output . sstrb pulses high for one clock period before the msb is clocked out. sstrb is high impedance when csn is high. 16 din serial data input . data is clocked in at the rising edge of sclk. 17 csn active-low chip select . data will not be clocked into pin din unless csn is low. when csn is high, pins dout and sstrb are high impedance. 18 sclk serial clock input . this pin clocks data into and out of the serial interface, and is used to set the conversion speed. note: the duty cycle must be between 40 and 60%. 19 v dd2 positive supply voltage 20 v dd1 positive supply voltage AS1530/ as1531 1 ch0 2 ch1 3 ch2 4 ch3 5 ch4 6 ch5 7 ch6 8 ch7 9 com 10 v dd3 20 v dd1 19 v dd2 18 sclk 17 csn 16 din 15 sstrb 14 dout 13 gnd 12 refadj 11 ref
www.austriamicrosystems.com revision 1.02 4 - 29 AS1530/as1531 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical character- istics on page 5 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments v dd1 , v dd2 , v dd3 to gnd -0.3 +7 v v dd1 to v dd2 to v dd3 -0.3 +0.3 v ch0:ch7, com to gnd -0.3 v dd1 + +0.3 v ref, refadj to gnd -0.3 v dd1 + +0.3 v din, sclk, csn, to gnd -0.3 v dd2 + +0.3 v dout, sstrb to gnd -0.3 v dd2 + +0.3 v dout, sstrb sink current 25 ma continuous power dissipation (t amb = +70oc) 559 mw derate 7.0mw/oc above +70oc operating temperature range -40 +85 oc storage temperature range -60 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com revision 1.02 5 - 29 AS1530/as1531 data sheet - electrical characteristics 6 electrical characteristics AS1530 electrical ch aracteristics v dd1 = v dd2 = v dd3 = +4.5 to +5.5v, com = gnd, f sclk = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t amb = t min to t max (unless otherwise specified). typ values at t amb = +25oc. table 3. AS1530 electrical characteristics symbol parameter conditions min typ max units dc accuracy 1 resolution 12 bits inl relative accuracy 2 -1 +1 lsb dnl differential nonlinearity no missing codes over temperature -1 +1 lsb offset error -6 +6 lsb gain error 3 -6 +6 lsb gain-error temperature coefficient 1.6 ppm/ c channel-to-channel offset error matching 0.2 lsb dynamic specifications : 100khz sinewave input, 2.5vp-p, 400ksps, 6.4mhz clock, bit range (page 15) = 0, pseudo-differential input mode sinad signal-to-noise plus distortion ratio 70 db thd total harmonic distortion up to the 5th harmonic -82 db sfdr spurious-free dynamic range 83 db imd intermodulation distortion f in1 = 99khz, f in2 = 102khz 76 db channel-to-channel crosstalk 4 f in = 200khz, v in = 2.5vp-p -85 db full-power bandwidth -3db point 6 mhz full-linear bandwidth sinad > 68db 450 khz conversion rate t conv conversion time 5 2.5 s t acq track/hold acquisition time 390 ns t ad aperture delay 7 ns t aj aperture jitter <50 ps f sclk serial clock frequency 0.5 6.4 mhz duty cycle 40 60 % analog inputs: ch0:ch7, com v chx - v chy (com) input voltage range: single- ended, pseudo-differential, and differential 6 bit range (page 15) = 1 0 v ref v bit range (page 15) = 0 -v ref /2 +v ref /2 multiplexer leakage current on/off leakage current, v chx = 0 or v dd1 -1 0.001 +1 a input capacitance 18 pf internal reference v ref ref output voltage t amb = +25oc 2.48 2.50 2.52 v ref short-circuit current 30 ma t cvref ref output temperature coefficient 25 ppm/ c load regulation 7 0 to 1ma output load 1.2 4.0 mv/ ma c bypref capacitive bypass at ref 4.7 10 f
www.austriamicrosystems.com revision 1.02 6 - 29 AS1530/as1531 data sheet - electrical characteristics c bypref adj capacitive bypass at refadj 0.01 10 f refadj output voltage 1.22 v refadj input range for small ad justments, from 1.22v 100 mv refadj buffer disable threshold to power down the internal reference 1.4 v dd1 - 1 v buffer voltage gain 2.045 v/v external reference : reference buffer disabled, reference applied to pin ref ref input voltage range 8 1.0 v dd1 + 50mv v ref input current v ref = 2.50v, f sclk = 6.4mhz 200 350 a v ref = 2.50v, f sclk = 0 320 power-down, f sclk = 0 5 digital inputs : din, sclk, csn v inh input high voltage 0.7 x v dd v v inl input low voltage 0.3 x v dd v v hyst input hysteresis 0.2 v i in input leakage v in = 0 or v dd2 -1 +1 a c in input capacitance 5 pf digital outputs : dout, sstrb v ol output voltage low i sink = 5ma 0.45 v v oh output voltage high i source = 1ma 4 v i l tri-state leakage current csn = v dd2 -10 +10 a c out tri-state output capacitance csn = v dd2 5 pf power supply v dd1 , v dd2 , v dd3 positive supply voltage 9 4.5 5.5 v i vdd1 , i vdd2 , i vdd3 supply current v dd1 = v dd2 = v dd3 = 5.5v normal operation with external reference 10 2.8 3.3 ma normal operation with internal reference 10 3.3 3.8 reduced-power mode 11 0.4 0.8 full power-down mode 0.5 2 a psr power-supply rejection v dd1 = v dd2 = v dd3 = 5v 10% -2 0.1 +2 mv 1. tested at v dd1 = v dd2 = v dd3 = +5v, com = gnd, bit range (page 15) = 1, single-ended input mode. 2. relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. offset nulled. 4. ground on channel; sinewave applied to all off channels. 5. conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. the absolute voltage range for the analog inputs (ch0:ch7, and com) is from gnd to v dd1 . 7. external load should not change during conversion for specified accuracy. guarantee d specification of 4mv/ma is a result of production test limitations. 8. AS1530/as1531 performance is limited by the device noise floor, typically 300vp-p. table 3. AS1530 electrical characteristics (continued) symbol parameter conditions min typ max units
www.austriamicrosystems.com revision 1.02 7 - 29 AS1530/as1531 data sheet - electrical characteristics as1531 electrical characteristics v dd1 = v dd2 = v dd3 = +2.7 to +3.6v, com = gnd, f sclk = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t amb = t min to t max (unless otherwise specified). typ values at t amb = +25oc. 9. electrical characteristics are guaranteed from v dd1(min) = v dd2(min) = v dd3(min) to v dd1(max) = v dd2(max) = v dd3(max) . for operations beyond this range, see typical operating characteristics on page 11 . for guaranteed specifications beyond the limits, contact austriamicrosystems, ag. 10. ain = mid-scale; bit range (page 15) = 1; tested with 20pf on dout, 20pf on sstrb, and f sclk = 6.4mhz @ gnd to v dd2 . 11. sclk = din = gnd, csn = v dd2 . table 4. as1531 electrical characteristics symbol parameter conditions min typ max units dc accuracy 1 resolution 12 bits inl relative accuracy 2 -1 +1 lsb dnl differential nonlinearity no missing codes over temperature -1 +1 lsb offset error -6 +6 lsb gain error 3 -6 +6 lsb gain-error temperature coefficient 1.6 ppm/ c channel-to-channel offset error matching 0.2 lsb dynamic specifications : 75khz sinewave input, 2.5vp-p, 300ksps, 4.8mhz clock, bit range (page 15) = 0, pseudo-differential input mode sinad signal-to-noise plus distortion ratio 70 db thd total harmonic distortion up to the 5th harmonic -81 db sfdr spurious-free dynamic range 84 db imd intermodulation distortion f in1 = 73khz, f in2 = 77khz 76 db channel-to-channel crosstalk 4 f in = 150khz, v in = 2.5vp-p -80 db full-power bandwidth -3db point 6 mhz full-linear bandwidth sinad > 68db 350 khz conversion rate t conv conversion time 5 normal operation 3.3 s t acq track/hold acquisition time normal operation 520 ns t ad aperture delay 7 ns t aj aperture jitter <50 ps f sclk serial clock frequency normal operation 0.5 4.8 mhz duty cycle 40 60 % analog inputs: ch0:ch7, com v chx - v chy (com) input voltage range: single- ended, pseudo-differential, and differential 6 bit range (page 15) = 1 0 v ref v bit range (page 15) = 0 -v ref /2 +v ref /2 multiplexer leakage current on/off leakage current, v chx = 0 or a vdd -1 0.001 +1 a input capacitance 18 pf internal reference v ref ref output voltage t amb = +25c 2.48 2.50 2.52 v ref short-circuit current 30 ma
www.austriamicrosystems.com revision 1.02 8 - 29 AS1530/as1531 data sheet - electrical characteristics t cvref ref output temperature coefficient 25 ppm/ c load regulation 7 0 to 0.75ma output load 0.6 2.0 mv/ ma c bypref capacitive bypass at ref 4.7 10 f c bypref adj capacitive bypass at refadj 0.01 10 f refadj output voltage 1.22 v refadj input range for small adjustments, from 1.22v 100 mv refadj buffer disable threshold to power down the internal reference 1.4 v dd1 - 1 v buffer voltage gain 2.045 v/v external reference : reference buffer disabled, reference applied to ref ref input voltage range 8 1.0 v dd1 + 50mv v ref input current v ref = 2.50v, f sclk = 4.8mhz 200 350 a v ref = 2.50v, f sclk = 0 320 in power-down, f sclk = 0 5 digital inputs : din, sclk, csn v inh input high voltage 0.7 x v dd v v inl input low voltage 0.3 x v dd v v hyst input hysteresis 0.8 v i in input leakage v in = 0 or v dd2 -1 +1 a c in input capacitance 5 pf digital outputs : dout, sstrb v ol output voltage low i sink = 5ma 0.45 v v oh output voltage high i source = 0.5ma v dd2 - 0.5v v i l tri-state leakage current csn = v dd2 -10 +10 a c out tri-state output capacitance csn = v dd2 5pf power supply v dd1 , v dd2 , v dd3 positive supply voltage 9 2.7 3.6 v i vdd1 , i vdd2 , i vdd3 supply current v dd1 = v dd2 = v dd3 = 5.5v normal operation with external reference 10 2.2 2.7 normal operation with internal reference 10 2.7 3.2 ma reduced-power mode 11 0.4 0.8 full power-down mode 11 0.5 2 a psr power-supply rejection v dd1 = v dd2 = v dd3 = 2.7 to 3.6v, mid-scale input -2 0.1 +2 mv 1. tested at v dd1 = v dd2 = v dd3 = +3v; com = gnd; bit range (page 15) = 1, single-ended input mode. table 4. as1531 electrical characteristics (continued) symbol parameter conditions min typ max units
www.austriamicrosystems.com revision 1.02 9 - 29 AS1530/as1531 data sheet - electrical characteristics timing characteristics 2. relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. offset nulled. 4. ground on channel; sinewave applied to all off channels. 5. conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. the absolute voltage range for the analog inputs (ch0:ch7, and com) is from gnd to v dd1 . 7. external load should not change during conversion for specified accuracy. guarant eed specification of 2mv/ma is a result of production test limitations. 8. AS1530/as1531 performance is limited by the device noise floor, typically 300vp-p. 9. electrical characteristics are guaranteed from v dd1(min) = v dd2(min) = v dd3(min) to v dd1(max) = v dd2(max) = v dd3(max) . for operations beyond this range, see typical operating characteristics on page 11 . for guaranteed specifications beyond the limits, contact austriamicrosystems, ag. 10. ain = mid-scale; bit range (page 15) = 1; tested with 20pf on dout, 20pf on sstrb, and f sclk = 4.8mhz @ gnd to v dd2 . 11. sclk = din = gnd, csn = v dd2 . table 5. AS1530 timing characteristics ? (figures 3 , 4 , 21 , 23 ; v dd1 = v dd2 = v dd3 = +4.5 to +5.5v; t amb = t min to t max (unless other wise specified). symbol parameter conditions min typ max units t cp sclk period 156 ns t ch sclk pulse width high 62 ns t cl sclk pulse width low 62 ns t ds din to sclk setup 35 ns t dh din to sclk hold 0 ns t css csn fall to sclk rise setup 35 ns t cs0 sclk rise to csn fall ignore 35 ns t doh sclk rise to dout hold c load = 20pf 10 20 ns t sth sclk rise to sstrb hold c load = 20pf 10 20 ns t stv sclk rise to dout valid c load = 20pf 80 ns t dov sclk rise to sstrb valid c load = 20pf 80 ns t dod csn rise to dout disable c load = 20pf 10 65 ns t std csn rise to sstrb disable c load = 20pf 10 65 ns t doe csn fall to dout enable c load = 20pf 65 ns t ste csn fall to sstrb enable c load = 20pf 65 ns t csw csn pulse width high 100 ns table 6. as1531 timing characteristics ? (figures 3 , 4 , 21 , 23 ; v dd1 = v dd2 = v dd3 = +2.7 to +3.6v; t amb = t min to t max (unless otherwise specified). symbol parameter conditions min typ max units t cp sclk period 208 ns t ch sclk pulse width high 83 ns t cl sclk pulse width low 83 ns t ds din to sclk setup 45 ns t dh din to sclk hold 0 ns t css csn fall to sclk rise setup 45 ns t cs0 sclk rise to csn fall ignore 45 ns t doh sclk rise to dout hold c load = 20pf 13 20 ns t sth sclk rise to sstrb hold c load = 20pf 13 20 ns
www.austriamicrosystems.co m revision 1.02 10 - 29 AS1530/as1531 data sheet - electrical characteristics figure 3. dout enable-time load circuits figure 4. dout disable-time load circuits t dov sclk rise to dout valid c load = 20pf 100 ns t stv sclk rise to sstrb valid c load = 20pf 100 ns t dod csn rise to dout disable c load = 20pf 13 85 ns t std csn rise to sstrb disable c load = 20pf 13 85 ns t doe csn fall to dout enable c load = 20pf 85 ns t ste csn fall to sstrb enable c load = 20pf 85 ns t csw csn pulse width high 100 ns table 6. as1531 timing characteristics ? (figures 3 , 4 , 21 , 23 ; v dd1 = v dd2 = v dd3 = +2.7 to +3.6v; t amb = t min to t max (unless otherwise s pecified). (continued) symbol parameter conditions min typ max units c load 20pf c load 20pf 6k gnd dgnd dout dout high-impedance to v oh and v ol to v oh v dd2 high-impedance to v ol and v oh to v ol 6k dgnd 6k c load 20pf c load 20pf 6k dgnd gnd dgnd dout dout v oh to high-impedance v dd2 v ol to high-impedance
www.austriamicrosystems.co m revision 1.02 11 - 29 AS1530/as1531 data sheet - typical operating characteristics 7 typical operating characteristics same conditions as stated in electrical characteristics on page 5 . figure 5. inl vs. digital output code figure 6. dnl vs. digital output code figure 7. fft @ 10khz; range = 1, mode = 1 f igure 8. fft @ 75khz; range = 0, mode = 1 figure 9. enob vs. v ref ; 1st order 300khz figure 10. enob vs. input signal frequency; 1st low pass filter order 1mhz low pass filter -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1000 2000 3000 4000 digital output code inl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1000 2000 3000 4000 digital output code dnl (lsb) . -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 20 40 60 80 100 120 140 160 input signal frequency (khz) fft (dbc) e -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 20 40 60 80 100 120 140 160 input signal frequency (khz) fft (dbc) e f sample = 312.5ksps n fft = 16384 f sample = 312.5ksps n fft = 16384 10.6 10.8 11 11.2 11.4 11.6 12345 voltage (v) enob (bit) . as1531: f sig = 75khz AS1530: f sig = 100khz 11.05 11.1 11.15 11.2 11.25 11.3 11.35 11.4 11.45 11.5 0 50 100 150 200 250 300 350 frequency (khz) enob (bit) .
www.austriamicrosystems.co m revision 1.02 12 - 29 AS1530/as1531 data sheet - typical operating characteristics figure 11. i vdd vs. v dd (static) figure 12. i vdd vs. temperature; internal reference figure 13. i vdd vs. v dd (converting) figure 14. i vdd vs. temperature (static) figure 15. v ref vs. temperature 2.5 2.75 3 3.25 3.5 3.75 4 -40 -15 10 35 60 85 temperature (c) supply current (ma) e AS1530 as1531 0 0.5 1 1.5 2 2.5 3 3.5 4 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 supply voltage (v) supply current (ma) e internal reference external reference 0 0.5 1 1.5 2 -40 -15 10 35 60 85 temperature (c) supply current (ma ) AS1530, reduced power mode, internal ref. as1531, reduced power mode, internal ref. AS1530, reduced power mode, external ref. as1531, reduced power mode, external ref. 0 0.5 1 1.5 2 2.5 3 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 supply voltage (v) supply current (ma) e normal operation; internal reference reduced power mode; internal reference reduced power mode; external reference 2.49 2.495 2.5 2.505 2.51 -40 -15 10 35 60 85 temperature (c) reference voltage (v) .
www.austriamicrosystems.co m revision 1.02 13 - 29 AS1530/as1531 data sheet - typical operating characteristics figure 16. offset error vs. temperat ure figure 17. offset error vs. v dd figure 18. gain error vs. temperat ure figure 19. gain error vs. v dd -1.8 -1.6 -1.4 -1.2 -1 -40 -15 10 35 60 85 temperature (c) offset error (lsb) . -1.8 -1.6 -1.4 -1.2 -1 2.7 3.4 4.1 4.8 5.5 supply voltage (v) offset error (lsb) . 0 1 2 3 4 5 -40 -15 10 35 60 85 temperature (c) gain error (lsb) e -3 -2 -1 0 1 2 3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v dd (v) gain error (lsb) e
www.austriamicrosystems.co m revision 1.02 14 - 29 AS1530/as1531 data sheet - detailed description 8 detailed description analog input the equivalent input circuit ( figure 20 ) shows the input architecture: track/hold circuitry, input multiplexer, input com- parator, switched-capacitor dac, and internal reference. a fl exible serial interface provides easy connections to vari- ous microprocessors. figure 20. equivalent input circuit the input tracking circuitry has a 6mhz small-signal bandwidth , thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals modulat ed at frequencies exceeding the AS1530/as1531 sampling rate. note: to avoid high-frequency signals being aliased into the fr equency band of interest, anti alias filtering is recom- mended input protection internal protection diodes (which clamp the analog input to v dd1 and gnd) allow the channel inputs to swing from (gnd to 0.3v) to (v dd1 + 0.3v) without damaging the dev ices. however, for accurate conversions near full scale, the inputs must not exceed v dd1 by more than 50mv or be lower than gnd by 50mv. note: if the analog input exceeds 50mv beyond the supply voltag e, do not allow the input current to exceed 2ma. track/hold the track/hold stage enters tracking mode on the rising edge of sclk which clocks in bit mode of the 8-bit control byte (see figure 21 on page 17 ). the track/hold stage enters hold mode on the falling clock edge after bit pd0 of the 8- bit control byte has been shifted in. the time required for the track/hold circuit to acquire an i nput signal is a function of how quickly the input capacitance is charged. if the input signal source impedance is high, the acquisition time lengt hens. the acquisition time (t acq ) is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired. t acq is never less than 390ns (AS1530) or 520ns (as1531), and is calculated by: tacq = 9(rs + rin)18pf (eq 1) where: : r in = 800 r s = the source impedance of the input signal. note: source impedances below 2k do not significantly affect the ac performance of the devices. + ? + comparator r in c switch 11pf c hold 13pf ? ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com ref ain+ c switch 11pf + c hold 13pf ? sample switch c switch includes all parasitics analog input multiplexer ain-
www.austriamicrosystems.co m revision 1.02 15 - 29 AS1530/as1531 data sheet - detailed description control register the control register on the as153 0/as1531 is a 8-bit, write-only register. data is written to this register using the csn, din and sclk pins. the control register format is shown in table 7 and the function of the bits are defined in table 8 . the AS1530/as1531 operating modes are selected by sending an 8- bit data word to the internal shift register via pin din. after pin csn is pulled low, the first logic 1 on pin din is interpreted as a start bit. a start bit is defined as one of the following: the first logic 1 bit clocked into pin din (with csn low) any time the AS1530/as1531 is idle, e.g., after v dd1 and v dd2 are applied. the first logic 1 bit clocked into pin din after bit 6 of a conversion in progress is clocked out of pin dout. figure 22 on page 17 shows the serial-interfa ce timing necessary to perform a conversion every 16 sclk cycles. if csn is tied low and sclk is continuous, gu arantee a start bit by first clocking in sixteen 0s. the fastest speed at which the devices can operate is 16 clocks per conver sion (with csn held low between conversions). analog input configuration table 7. control byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start (msb) sel2 sel1 sel0 range mode pd1 pd0 (lsb) table 8. bit descriptions bit name description 7 start the first logic 1 bit after csn goes low signifies the start of a control byte. 6:4 sel2:sel0 these three bits select which of the eight channels and pin com are used for the conversion (see table 10 and table 11 ). 3 range this bit selects the analog input range of the AS1530/as1531. 0 = the analog input range extends from -v ref /2 to +v ref /2. 1= the analog input range extends from 0v to v ref . 2 mode this bit in conjunction with bit range changes the analog input configuration. 0 = the voltage difference between two selectable channels is converted. this setting selects two's complement coding (see table 10 on page 16 and table 11 on page 16 ). 1 = one of the eight input channels is re ferenced to com. this setting also selects binary coding. 1:0 pd1:pd0 selects the AS1530/as1531 operating mode: pd1 pd0 mode 0 0 full power-down mode. 0 1 reduced-power mode. 1 0 reduced-power mode. 1 1 normal operation. table 9. analog input configuration analog input configuration mode range coding comments 8-channel single-ended 1 1 binary ain+ from 0 to v ref . com should be tied to gnd. 8-channel pseudo differential referenced to com 1 1 binary ain+ from com to com + v ref 8-channel pseudo differential referenced to com 1 0 binary ain+ from -v ref /2+com to + v ref /2+com 4-channel pseudo differential 0 1 two's complement ain+ - ain- from 0 to v ref 4-channel pseudo differential 0 0 two's complement ain+ - ain- from -v ref /2 to +v ref /2 4-channel fully differential 0 0 two's complement ain+ - ain- from -v ref /2 to +v ref /2, fully differential input signal.
www.austriamicrosystems.co m revision 1.02 16 - 29 AS1530/as1531 data sheet - detailed description channel selection depending on the setting of bit mode (page 15) , the internal inputs of the adc (ain+ and ain-) are connected differ- ently to the input channels (ch0:ch7 and com). single-ended input note: in single-ended mode pin com should be connected to gnd pin. differential input table 10. input channel selection for mode = 1 sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0 0 0 ain+ ain- 0 0 1 ain+ ain- 0 1 0 ain+ ain- 0 1 1 ain+ ain- 1 0 0 ain+ ain- 1 0 1 ain+ ain- 1 1 0 ain+ ain- 1 1 1 ain+ ain- table 11. input channel selection for mode = 0 sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 0 0 0 ain+ ain- 0 0 1 ain+ ain- 0 1 0 ain+ ain- 0 1 1 ain+ ain- 1 0 0 ain- ain+ 1 0 1 ain- ain+ 1 1 0 ain- ain+ 1 1 1 ain- ain+
www.austriamicrosystems.co m revision 1.02 17 - 29 AS1530/as1531 data sheet - detailed description starting a conversion a conversion is started by clocking a control byte into pin din. with csn low, each risi ng edge on sclk clocks a bit from di n into the in ternal shift register, st arting with the msb. a conversion will only start when a logic 1 is written to the start bit of the 8-bit control register. figure 21. single conversion timing waveforms figure 22. continuous 16-clock conversion timing waveforms range b11 b10 b9 b8 b7 b0 b1 b2 b3 b4 b5 b6 t acq rb1 rb2 rb3 single conversion acquire idle idle 1 4 8 9 12 20 16 24 start high-z high-z high-z high-z csn sclk din sstrb dout sel2 sel1 sel0 mode pd0 pd1 high-z csn din sstrb sclk b11 b11 b0 b6 b6 b6 b0 ... conversion result 0 conversion result 1 control byte 0 control byte 1 control byte 2 high-z b11 112 8161 12 8161 12 816 ssss dout conversion result 2
www.austriamicrosystems.co m revision 1.02 18 - 29 AS1530/as1531 data sheet - detailed description figure 23. detailed serial interface timing waveforms the external serial clock shifts data in and out of the dev ices and drives the analog-to-digital conversion steps. two clock periods after the last bit of the control byte is written the output pin sstrb pulses high for one clock period. the serial data is shifted out at dout on each of the next 12 sclk rising edges (see figure 21 on page 17 ). pins sstrb and dout go into a high-impedance state when csn goes high. the conversion must complete in 120s or less, or consequently, droop on the sample-and- hold capacitors may degrade conversion results. figure 23 shows detailed serial-interface timing waveforms. transfer functions output coding and transfer function depend on the control register bits mode (page 15) and range (page 15) . figure 24. straight binary transfer function for figure 25. straight binary transfer function for range = 1 and mode = 1 range = 0 and mode = 1 t dh csn sclk din sstrb dout t css t cp t csw t cso t cl t ch t doh t dov t dod t std t sth t ds t doe t ste t stv 11...111 11...1110 11....101 00...011 00...010 00...001 00...000 output code 0123 input voltage ain+ - ain- (lsb) fs - 3/2lsb full scale (fs) transition full scale = v ref zero scale = 0 1lsb = v ref /4096 11...111 11...1110 11....101 00...011 00...010 00...001 00...000 output code zs zs+1lsb input voltage ain+ - ain- (lsb) fs - 3/2lsb full scale (fs) transition full scale = +v ref /2 zero scale = -v ref /2 1lsb = v ref /4096
www.austriamicrosystems.co m revision 1.02 19 - 29 AS1530/as1531 data sheet - detailed description figure 26. two?s complement transfer function for fi gure 27. two?s complement transfer function for range = 1 and mode = 0 range = 0 and mode = 0 power modes power consumption can be reduced by placing the AS1530/as1531 in reduced power mode or in full power-down mode between conversions. the power mode is selected using bits pd1 and pd0 of the 8-bit control byte. table 12 lists the three operating modes with the corresponding supply current and active device circuits. for data rates achievable in full power-down mode see full power-down mode on page 20 . * circuit operation between conversions; during conversion all circuits are fully powered up. the selected power-down mode (as shown in table 12 ) is initiated after an analog-to-digital conversion is completed. in all power modes the serial interfac e remains active, waiting for a new control byte to start conversion (see figure 30 on page 21 ). once the conversion is comple ted, the AS1530/as1531 goes into t he selected power mode until a new control byte is shifted in. in reduced power mode the as 1530/as1531 will be able to start conversion immediately when running at decreased clock rates. in full power down m ode wait until the internal reference has stabilized (depen- dant on the values of the capacitance of ref and refadj). during initialization the AS1530/as1531 immediately go into normal operation mode and are ready to convert after 4s when using an external reference. when using the internal re ference, wait until the inte rnal reference has stabilized (dependant on the values of the capacitance of ref and refadj). table 12. software controlled power modes pd1/pd0 (page 23) mode total supply current device circuits * during conversion after conversion input comparator reference AS1530 as1531 AS1530 as1531 00 full power-down mode 2.8ma 2.2ma 0.5a 0.5a off off 01 reduced-power mode 2.8ma 2.2ma 0.4ma 0.4ma reduced power on 10 11 normal operation 2.8ma 2.2ma 2.0ma 1.8ma full power on 011....111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 output code -fs zs input voltage ain+ - ain- (lsb) +fs - 1lsb full scale = v ref -full scale = 0 zero scale = v ref /2 1lsb = v ref /4096 011....111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 output code -fs zs input voltage ain+ - ain- (lsb) +fs - 1lsb full scale = +v ref /2 -full scale = -v ref /2 zero scale = 0 1lsb = v ref /4096
www.austriamicrosystems.co m revision 1.02 20 - 29 AS1530/as1531 data sheet - detailed description reduced power mode reduced power mode is activated using bits pd1 and pd0 (see table 12) . when reduced power mode is asserted, the AS1530/as1531 completes any conversion in progress and enters reduced power mode. the next start of conversion puts the AS1530/as1531 into no rmal operation mode. the 8-bit control byte shifted into the control register determines the next power mode. for exam ple, if the 8-bit control byte contains pd1 = 0 and pd0 = 1, reduced power mode starts i mmediately after the conversion (see figure 28 ) . the reduced-power mode achieves the lowest power consumption at speeds close to the maximum sample rate. figure 29 shows the as1531 power consumption in r educed-power mode and normal operating mode (see table 12 on page 19) with the internal reference and maximum clock speed. figure 28. reduced-power mode timing waveforms (as1531) note: the clock speed in reduced-power mode should be limited to 4.8mhz. full power-down mode may provide increased power savings in applications where the devices are inactive for long periods of time, where intermit- tent bursts of high-speed conversions are required. figure 29. normal operation and reduced powe r mode using internal reference (as1531) full power-down mode full power-down is activated using bits pd1 and pd0 (see table 12) . full power-down mode offers the lowest power consumption at up to 1000 conversions per-channel pe r-second. when full power-down is asserted, the AS1530/ as1531 completes any conversion in progress and powers down into specified low-quiescent current state. the start of the next conversion puts the AS1530/as1531 into normal operation mode. the 8-bit control byte shifted into the control register determines the next power mode. fo r example, if the 8-bit control byte contains pd1 = 0 and pd0 = 0, full power-down mode starts immediately after the conversion (see figure 30 on page 21 ) din 1 v dd1 +v dd2 +v dd3 11111 000 reduced- power mode reduced- power mode reduced- power mode 2.50v (always on) 2.2ma 2.2ma 2.2ma 0.4ma 0.4ma 0.4ma ref normal mode conversion reduced power mode normal mode conversion reduced power mode normal mode conversion reduced power mode 0 500 1000 1500 2000 2500 3000 0.001 0.1 10 1000 sampling rate (ksps) supply current (a) . reduced power mode normal operation
www.austriamicrosystems.co m revision 1.02 21 - 29 AS1530/as1531 data sheet - detailed description a 0.01f bypass capacitor plus the internal 17k reference resistor at refadj form an r/c filter with a 170s time constant. to achieve full 12-bit accuracy, 9 time constants (1.8ms) are required after power-up if the bypass capacitor is fully discharged between conversions. waiting this 1. 8ms in reduced-power mode instead of normal operation mode can further reduce power consumption. this is achieved by using the sequence shown in figure 30 on page 21 . figure 31 on page 21 shows the as1531 power consumption for conversions using full power-down mode (pd1 = pd0 = 0 (see table 12) , an external reference, and the maximum clock speed. one dummy conversion to power-up the device is required, but no wait-time is necessary to st art the second conversion, thereby achieving lower power con- sumption up to the full sampling rate. figure 30. full power-down timing waveforms (as1531) figure 31. average supply current vs. sampling ra te (as1531, fullpd, and external reference) reference the AS1530/as1531 can operate with the internal or an external reference. internal reference the internal reference is selected by placing a capacitor between refadj and gnd. the internally trimmed 1.22v bandgap voltage available at refadj is buffered with a gain of 2.045v/v to pin ref, where 2.5v are available. a decoupling capacitor is needed at pin ref. din 1 01110 000 full power- down reduced- power mode ref 1 refadj i vdd1 +i vdd2 +i vdd3 full power- down 1.22v 2.5v 2.2ma 2.2ma 2.2ma 2.5v 1.22v 0ma 0ma 0.4ma = r/c = 17 k x 0.01f full power- down normal mode conversion normal mode dummy conversion reduced power mode normal mode conversion full power- down 1 channel 0.1 100 100000 0.001 0.01 0.1 1 10 100 sampling rate (ksps) supply current (a) .
www.austriamicrosystems.co m revision 1.02 22 - 29 AS1530/as1531 data sheet - detailed description additionally the bandgap voltage can be adjusted about 100mv by forcing a voltage to the refadj pin. the refadj input impedance is typically 17k . figure 32 shows a possible arrangement. figure 32. reference adjust circuit external reference an external reference can be connected directly at pin ref. to use the external reference, the internal buffer must be disabled by connecting pin refadj to pin vdd. the input resistance is typically 15k . during conversion, an external reference at pin ref must deliver up to 350a dc load current and have 10 or less output impedance. if the reference has a higher output impedance or is noisy, bypass it with a 4.7f capacitor placed as close to pin ref as possible. note: using the refadj input makes buffering the external reference unnecessary. c load 0.01f gnd 100k dgnd 24k 510k +3.3v 12 refadj AS1530/ as1531
www.austriamicrosystems.co m revision 1.02 23 - 29 AS1530/as1531 data sheet - application information 9 application information initialization when power is first applied to the AS1530/as1531 internal power-on reset circuitry sets the devices for normal opera- tion. at this point, the devices can perf orm data conversions with csn held low. note: the device requires 10s after the power supplies stabiliz e; no conversions should be initiated during this time. the digital output at pin dout will be all 0s until an analog-to-digital conversion is initiated. serial interface the AS1530/as1531 fully support spi, qspi, and microwire interfaces. for spi, select the correct clock polarity and sampling edge in the spi control registers (set cpol = 0 and cpha = 0). note: microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the circuit shown in figure 33 on page 24 , the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the AS1530/as1531, and two more 8-bit transfers to clock out the 12-bit conversion result). serial interface configuration the following steps describe how to configure the serial interface: 1. confirm that the cpu serial interface is in master mode (so the cpu generates the serial clock). 2. choose a clock frequency from 500khz to 6.4mhz (AS1530) or 4.8mhz (as1531). 3. set up the control byte and call it tb1. tb1 should be in the format 1xxxxxxx binar y, where the xs indicate the selected channel, conversion mode, and power mode. 4. use a general-purpose i/o line on the cpu to pull csn low. 5. transmit tb1 and simultaneously receive a byte (rb1). ignore this byte. 6. transmit a byte of all zeros ($00 h ) and simultaneously receive byte rb2. 7. transmit a byte of all zeros ($00 h ) and simultaneously receive byte rb3. 8. pull csn high. bytes rb2 and rb3 (see figure 21 on page 17 ) contain the results of the conversion, padded with three leading zeros and one trailing zero. the total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. to avoid excessive track/hold droop, make sure the total conversion time does not exceed 120s.
www.austriamicrosystems.co m revision 1.02 24 - 29 AS1530/as1531 data sheet - application information figure 33. operational diagram qspi interface the AS1530/as1531 can interface with qspi using the circuit in figure 34 (f sclk = 4.0mhz, cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conversion on eac h of the eight channels. the result is stored in memory without affecting cpu performance, since qspi incorporates a micro-sequencer. figure 34. qspi interface connections +2.5v analog inputs 0.1f 12 refadj 20 v dd1 4.7f 1 ch0 19 v dd2 13 gnd 17 csn 14 dout 15 sstrb cpu v dd i/o 18 sclk 16 din sck (sk) mosi (so) miso (si) v ss 0.1f +3 to +5v 11 ref AS1530/ as1531 10 v dd3 . . . 8 ch7 9 com 10f +2.5v analog inputs 0.1f 12 refadj 11 ref 4.7f 1 ch0 8 ch7 13 gnd 14 dout 15 sstrb cpu pcso sck mosi miso gnd 0.1f 17 csn 16 din 18 sclk + 10f power supplies +3 or +5v +3 or +5v AS1530/ as1531 20 v dd1 19 v dd2 10 v dd3 . . . 9 com
www.austriamicrosystems.co m revision 1.02 25 - 29 AS1530/as1531 data sheet - application information quick evaluation circuit in order to quickly evaluate the analog performance of the AS1530/as1531, use the circuit shown in figure 35 . figure 35. evaluation circuit diagram connecting din to v dd2 shifts in control bytes of $ff h , which trigger single-ended conversions (bit range (page 15) = 1) on ch7 without powering down between conversions. the sstrb output pulses high for one clock period before the msb of the 12-bit conversion result is shifted out of dout. varying the analog input to ch7 will alter the sequence of bits from dout. a total of 16 clock cycles is required per conversion. note: all sstrb and dout output transitions occur 25ns (typ) after the rising edge of sclk. +2.5v analog input 0.1f 12 refadj 11 ref 4.7f 13 gnd 17 csn 14 dout 15 sstrb 18 sclk 16 din 0.1f to v dd2 0.1f 10f +3 or +5v external clock 8 ch7 AS1530/ as1531 tba 20 v dd1 19 v dd2 10 v dd3 9 com
www.austriamicrosystems.co m revision 1.02 26 - 29 AS1530/as1531 data sheet - application information layout considerations the AS1530/as1531 require proper layout and design procedures for optimum performance. use printed circuit boards; wirewrap boards should not be used. analog and digital traces should be separate and should not run parallel to each other (especially clock traces). digital traces should not run beneath the AS1530/as1531. use a single-point analog ground at gnd, separate from the digital ground (see figure 36 ). connect all other ana- log grounds and dgnd to this star ground point for further noise reduction. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the AS1530/as1531 high-speed comparator. bypass this supply to the single-point analog ground with 0.1f and 4.7f bypass capacitors. bypass capacitors should be as close to the device as possible for optimum power supply noise-rejection. if the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise (see figure 36 ). figure 36. recommended gnd design power supplies digital circuitry + + 10 (optional) 9 com v dd1 gnd gnd v dd2 dgnd v dd 19 v dd2 13 gnd 20 v dd1 AS1530/ as1531 10 v dd3
www.austriamicrosystems.co m revision 1.02 27 - 29 AS1530/as1531 data sheet - package drawings and markings 10 package drawings and markings figure 37. 20-pin tssop package symbol min typ max notes a--1.101,2 a1 0.05 - 0.15 1,2 a2 0.85 0.90 0.95 1,2 l 0.50 0.60 0.75 1,2 r0.09- -1,2 r1 0.09 - - 1,2 b 0.19 - 0.30 1,2,5 b1 0.19 0.22 0.25 1,2 c 0.09 - 0.20 1,2 c1 0.09 - 0.16 1,2 1 0o - 8o 1,2 l1 1.0ref 1,2 aaa 0.10 1,2 bbb 0.10 1,2 ccc 0.05 1,2 ddd 0.20 1,2 e 0.65bsc 1,2 212oref1,2 312oref1,2 variations d 6.40 6.50 6.60 1,2,3,8 e1 4.30 4.40 4.50 1,2,4,8 e 6.4bsc 1,2 e 0.65bsc 1,2 n 20 1,2,6 notes: 1. all dimensions are in millimeters; angles in degrees. 2. dimensioning and tolerancing per asme y14.5m ? 1994 . 3. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusions shall not exceed 0.25mm per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 6. terminal numbers are for reference only. 7. datums a and b to be determined at datum plane h. 8. dimensions d and e1 are to be determined at datum plane h. 9. this dimension applies only to variations with an even number of leads per side. 10. cross section a-a to be determined at 0.10 to 0.25mm from the leadtip.
www.austriamicrosystems.co m revision 1.02 28 - 29 AS1530/as1531 data sheet - ordering information 11 ordering information the devices are available as the standard products shown in table 13 . table 13. ordering information model description delivery form package AS1530-t 12-bit adc, 8-channel, 400ksps tape and reel 20-pin tssop AS1530 12-bit adc, 8-channel, 400ksps tubes 20-pin tssop as1531-t 12-bit adc, 8-channel, 300ksps tape and reel 20-pin tssop as1531 12-bit adc, 8-channel, 300ksps tubes 20-pin tssop
www.austriamicrosystems.co m revision 1.02 29 - 29 AS1530/as1531 data sheet copyrights copyright ? 1997-200 7, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used without the prio r written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environ mental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specif ically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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